Compiling Hume down to gates

We describe the implementation of a subset of the Hume programming language on a FPGA architecture at the gate level. Hume is a domain specific language for developping multi-process systems requiring strong static guarantees that resource bounds are met. The compiler produces RT-level, synthetizable VHDL code that can be processed by a standard tool chain to program FPGAs at the gate level. Preliminary results suggest that this compilation route offers substantial opportunities for exploiting fine-grain parallelism in Hume programs. The approach also offers an significantly higher abstraction level than that offered by traditional hardware description languages such as VHDL or Verilog.